『徳島大学 教育・研究者情報データベース (EDB)』---[学外] /
〔閲覧〕【著作】
--- テーブル「著作」（著作（著書，論文，レター，国際会議など））は研究業績にかかる著作（著書，論文，レター，国際会議など）を登録するテーブルです．
登録情報
抽出条件
| OWN= |  橋爪 正樹
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登録情報の数
有効な情報: 251件 + 無効な情報: 9件 = 全ての情報: 260件
全ての有効な情報 (251件)
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抽出結果のリスト
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排列順: 項目表示: 橋爪 正樹, 森田 郁朗, 荒瀬 友子 : 脳波解析による麻酔深度の推定, 電子通信学会論文誌(D), Vol.J67-D, No.8, 892-899, 1984年. ... 橋爪 正樹, 山本 博資, 為貞 建臣, 埴渕 敏明 : 内容検索メモリの性能評価, 電子情報通信学会技術研究報告, Vol.EC84, No.50, 1-11, 1985年(0月). ... Masaki Hashizume, Ikuro Morita and Hiroshi Okitsu : Estimating the Level of Anesthesia by EEG Analysis, Systems and Computers in Japan, Vol.16, No.1, 42-52, 1985. ... 山本 博資, 橋爪 正樹 : パソコンによるLisp入門, 森北出版, (都市), 1985年7月. ... 橋爪 正樹, 阿部 昭人 : パソコン上で実行可能なmicro-VALIDの試作, bit, Vol.16, No.11, 83-87, 1985年11月. ... 橋爪 正樹, 山本 博資 : muLISP-85とWaltz Lispの徹底比較, 日経バイト, (巻), No.18, 145-157, 1986年(0月). ... 平野 収三, 橋爪 正樹, 為貞 建臣 : マイクロコンピュータの編集設計システムの試作, 情報処理学会設計自動化研究会, Vol.DA-34, No.5, 1-8, 1986年(0月). ... 山本 博資, 橋爪 正樹 : パソコンによるLisp入門-増補版-, 森北出版, (都市), 1986年7月. ... 桝田 真喜夫, 山田 和浩, 橋爪 正樹, 為貞 建臣 : 電源電流波形による論理回路の故障診断法, 電子情報通信学会技術研究報告, Vol.FTS-87, No.16, 5-10, 1987年(0月). ... 井下 順功, 橋爪 正樹, 為貞 建臣 : 回路モジュールのタイミングチャートを利用した論理シミュレータ, 電子情報通信学会技術研究報告, Vol.VLD-87, No.103, 45-52, 1987年(0月). ... 橋爪 正樹, 山本 博資, 為貞 建臣, 埴渕 敏明 : 内容検索メモリを用いた検索システムの速度性能の評価, 電子情報通信学会論文誌(D), Vol.J70-D, No.9, 1709-1717, 1987年. ... H. Y. Kawai, Masaki Hashizume and Takeomi Tamesada : A Tr-Amplifier Design Utilizing a Circuit Simulator, IEICE Technical Report, Vol.CAS-88, No.69, 67-73, (month)1988. ... 山田 和浩, 橋爪 正樹, 為貞 建臣, 河上 正明 : 電源電流による組合せ回路の故障検出法, 電子情報通信学会技術研究報告, Vol.VLD-88, No.55, 1-8, 1988年(0月). ... 橋爪 正樹, 山本 博資, 為貞 建臣, 高橋 一磨 : 樹枝状に分割可能な組合せ回路の故障検出入力生成法, 情報処理学会論文誌, Vol.29, No.6, 627-630, 1988年. ... 橋爪 正樹, 桝田 真喜夫, 山田 和浩, 為貞 建臣 : 自己回帰モデルを用いた電源電流波形による論理回路の故障診断法, 電子情報通信学会論文誌(D), Vol.J71-D, No.9, 1804-1814, 1988年. ... 橋爪 正樹, 為貞 建臣 : TTL組合せ論理回路の電源電流による故障検出法, 電子情報通信学会論文誌(D), Vol.J73-D-I, No.7, 621-629, 1990年. ... 橋爪 正樹, 為貞 建臣, 山田 和浩 : TTL組合せ論理回路の故障検出のための電源電流標準パターン候補導出法, 電子情報通信学会論文誌(D-I), Vol.J73-D-I, No.7, 637-640, 1990年. ... 橋爪 正樹, 為貞 建臣, 新居 浩二 : 凸ファジー決定によるアナログ回路の回路定数最適化法, 電子情報通信学会論文誌(D), Vol.J73-A, No.8, 1350-1358, 1990年. ... 橋爪 正樹, 為貞 建臣, 新居 浩二 : 下限満足度制約をもつファジィ多目的計画問題の近似的満足解導出法, 電子情報通信学会論文誌(D), Vol.J74-D-I, No.2, 109-116, 1991年. ... Masaki Hashizume, Tasaka Eiji, Takeomi Tamesada, Kayahara Toshihiro and Yamazoe Tomohisa : A Practical Functional Test Using Flowchart for Production Testing of Microprocessor Based Sequence Controllers, Transactions of the IEICE of Japan, Vol.E76-D, No.7, 837-841, 1993. ... Masaki Hashizume, Takeomi Tamesada and Koji Nii : Fuzzy Multiobjective Satisficing Programming Utilizing Expertise Knowledge, Fuzzy Optimization Recent Advances, (巻), (号), 220-233, 1994. ... Masaki Hashizume, Y. Iwata and Takeomi Tamesada : Performance Evaluation for Fault Detection of Analog Electronic Circuits, Fuzzy Logic and Its Applications to Engineering, (巻), (号), 255-264, 1995. ... 橋爪 正樹, 為貞 建臣, 森田 郁朗 : 上肢切断者のための顔面方位による計算機への入力キー選択法, 第14回バイオメカニカルシンポジウム, 175-184, 1995年7月. ... 橋爪 正樹, 矢野 武志, 口井 敏匡, 為貞 建臣 : 電流テストによるバイポーラ組合せ論理回路のブリッジ故障検出のための検査容易化設計法, 電子情報通信学会論文誌(D-I), Vol.J79-I, No.12, 1092-1104, 1996年. ... Toshihiro Sezaki, Masaki Hashizume, Takeomi Tamesada and Ikuro Morita : Supply Current Measurement Circuit for Bridging Fault Detection in Microprocessor Based Circuit, Proceedings of ITC-CSCC'97 International Technical Conference on Circuits Systems, Computers and Comunications, 935-938, Okinawa, July 1997. ... 口井 敏匡, 橋爪 正樹, 為貞 建臣 : プリント回路板上のTTL組み合わせ回路の電源電流による断線故障検出法, エレクトロニクス実装学会誌, Vol.1, No.4, 284-293, 1998年. ... Masaki Hashizume, Takeomi Tamesada, Takeshi Koyama and Goor de A.J.van : CMOS SRAM Functional Test with Quiescent Write Supply Current, Proc. of the IEEE International Workshop on IDDQ Testing, (巻), (号), 4-8, San Jose, Nov. 1998. ... Toshimasa Kuchii, Masaki Hashizume and Takeomi Tamesada : Test Input Generation for Supply Current Testing of Bridging Faults in Bipolar Combinational Logic Circuits, Proc. of the IEEE International Workshop on IDDQ Testing, (巻), (号), 14-18, San Jose, Nov. 1998. ... Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada and Kozo Kinoshita : A High Speed IDDQ Sensor for Low Voltage ICs, IEEE Seventh Asian Test Symposium, (巻), (号), 327-331, Singapore, Dec. 1998. ... 橋爪 正樹, 為貞 建臣, 小山 健, A.J. van de Goor : CMOS SRAM ICの書き込み時静的電源電流による論理故障検出法, 電子情報通信学会論文誌(D-I), Vol.J82-D-I, No.7, 906-915, 1999年. ... Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara : Supply Current testing for Bridging Faults in Microprocessor Based Sequence Control Circuits, Proc. of Electronic Circuits World Convention 8, (巻), (号), 31-37, Tokyo, Sep. 1999. ... Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Identification of Feedback Bridging Faults with Oscillation, IEEE Eighth Asian Test Symposium, (巻), (号), 25-30, Shanghai, Nov. 1999. ... Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Testable Design of Static CMOS PLAs, IEEE International Workshop on Defect Based Testing, (巻), (号), 70-75, Montreal, April 2000. ... Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Masashi Takeda : Testability Analysis of IDDQ Testing with Large Threshold Value, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, (巻), (号), 367-375, Yamanashi Japan, Oct. 2000. ... Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada and Masashi Takeda : High Speed IDDQ Test and Its Testability for Process Variation, IEEE Asian Test Symposium, (巻), (号), 344-349, TAIPEI TAIWAN, Dec. 2000. ... Masaki Hashizume, Masahiro Ichimiya, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Defect Detection by Supply Current Test, Proc. of Design, Automation and Test in Europe Conference 2001, (巻), (号), 509-513, Munich, March 2001. ... Masaki Hashizume, Nobuyuki Inou, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation for Detecting Feedback Bridging Faults, Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, (号), 1980-1983, Phuket, Thailand, July 2002. ... Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Pin Open in Small Outline Package ICs by Supply Current Test, Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications, (巻), (号), 832-835, Kang-Won Do, Korea, July 2003. ... 橋爪 正樹, 田坂 英司, 四柳 浩之, 為貞 建臣, 茅原 敏広, 森田 郁朗, 大家 隆弘 : CMOSマイクロコンピュータ回路の電源電流によるブリッジ故障検出法, エレクトロニクス実装学会誌, Vol.6, No.7, 564-572, 2003年. ... 森田 郁朗, 橋爪 正樹 : PSpiceによる三相HB形ステッピングモータの駆動特性解析, 電気学会論文誌D (産業応用部門誌), Vol.D-124, No.4, 423-424, 2004年. ... Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Tsukimoto Isao and Takeomi Tamesada : AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs, Proc. of International Conference on Electronics Packaging, (巻), (号), 217-222, Tokyo, April 2004. ... Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application, Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems, (巻), (号), I-557-I-560, Hiroshima, July 2004. ... Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Vectorless Open Pin Detection Method for CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, (巻), (号), 391-396, Tokyo, April 2005. ... 月本 功, 橋爪 正樹, 四柳 浩之, 為貞 建臣 : ばらつきを有するICで構成したTTL回路の電源電流による統計的断線故障検出法, エレクトロニクス実装学会誌, Vol.8, No.3, 199-207, 2005年. ... Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing, Proc. of IEEE International Symposium on Circuits and Systems, (巻), (号), 2995-2998, Kobe, May 2005. ... Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application, Proceedings of ICEP2006, (巻), (号), 147-152, Tokyo, April 2006. ... Ono Akira, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Open Lead Detection of CMOS Logic Circuits by Low Pressure Probing, Proceedings of ICEP2007, 359-364, Tokyo, April 2007. ... 高木 正夫, 橋爪 正樹, 一宮 正博, 四柳 浩之 : 交流電界印加時の電流テストによるCMOS LSIのリード浮き検出のための印加交流電圧, エレクトロニクス実装学会誌, Vol.10, No.3, 219-228, 2007年. ... 橋爪 正樹, 一宮 正博, 四柳 浩之 : CMOS QFP ICのリード浮きの電気的検査法, アカデミック・ラボラトリ・ポスタープログラム講演論文集, 41-46, 2007年6月. ... 小野 安季良, 一宮 正博, 四柳 浩之, 橋爪 正樹, 月本 功, 高木 正夫 : 論理IC実装時に発生する抵抗を伴うリード浮きに対する電流テスト能力評価, マイクロエレクトロニクスシンポジウム, 195-198, 2007年9月. ... Masaki Hashizume, Masahiro Ichimiya, Akira Ono and Hiroyuki Yotsuyanagi : Test Circuit for Vectorless Open Lead Detection of CMOS ICs, IEEE 6-th International Board Test Workshop, Fort Collins, Oct. 2007. ... 小野 安季良, 一宮 正博, 四柳 浩之, 高木 正夫, 橋爪 正樹 : 電流テストによるQFP CPLD ICのリード浮きの検査能力評価, 第22回エレクトロニクス実装学会講演大会, 143-144, 2008年3月. ... Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Test Method for DetectingOpen Leads of Low Voltage LSIs, Proceedings of ICEP2008, 457-462, Tokyo, June 2008. ... Masaki Hashizume, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Fault Analysis of Interconnect Opens in 90nm ICs with Device Simulator, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 249-252, Shimonoseki, Japan, July 2008. ... Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 241-244, Shimonoseki,Japan, July 2008. ... Yutaka Hata, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura : Current Testble Design of Resistor String DACs for Open Defects, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 1533-1536, Shimonoseki, Japan, July 2008. ... Masaki Hashizume, Akihito Shimoura, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Test Circuit for Locating Open Leads of QFP ICs, IEEE 7-th International Board Test Workshop, Fort Collins, USA, Sep. 2008. ... Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Novel Approach for Improving the Quality of Open Fault Diagnosis, Proc. of 22nd International Conference on VLSI Design, 85-90, New Delhi, India, Jan. 2009. ... Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC, Proc. of 22nd International Conference on VLSI Design, 91-96, New Delhi, India, Jan. 2009. ... 小野 安季良, 一宮 正博, 四柳 浩之, 高木 正夫, 橋爪 正樹 : CMOSゲート回路を断線センサとして用いた部品接合不良検出法, エレクトロニクス実装学会誌, Vol.12, No.2, 137-143, 2009年. ... 小野 安季良, 一宮 正博, 四柳 浩之, 高木 正夫, 橋爪 正樹 : 検査回路の電源電流測定によるICの電源リード浮き検査能力評価, エレクトロニクス実装学会講演大会講演論文集, 79-80, 2009年3月. ... 橋爪 正樹, 一宮 正博, 四柳 浩之, 小野 安季良, 高木 正夫 : QFP ICのリード浮きの電気的検出用回路, 第23回エレクトロニクス実装学会講演大会, (巻), (号), 75-77, 2009年3月. ... 飯田 仁, 橋爪 正樹 : 学生証による出席管理のためのICカードリーダーの試作, 大学教育研究ジャーナル, No.6, 70-74, 2009年. ... Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Lead Detection of QFP ICs Using Logic Gates as Open Sensors, Proc. of 2009 International Conference on Electronics Packaging, 434-439, Kyoto,Japan, April 2009. ... Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : Current Testable Design of Resistor String DACs for Short Defects, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 428-431, Jeju,Korea, July 2009. ... Toshiyuki Tsutsumi, Yasuyuki Kariya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Preliminary Analysis of Interconnect Full Open Faults using TEG chips, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 679-682, Jeju, Korea, July 2009. ... Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 794-796, Jeju,Korea, July 2009. ... 橋爪 正樹, 内倉 健一, 小野 安季良, 四柳 浩之, 高木 正夫 : IC内組込型インターコネクトオープン検出回路, 第24回エレクトロニクス実装学会講演大会, 48-49, 2010年3月. ... Shohei Kondo, Katsuya Manabe, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Faulty Effects on Logic Signal of a Hard Open Via from Adjacent Ones, Proceedings of ICEP2010, 711-715, Sapporo, Japan, April 2010. ... Masaki Hashizume, Kenichi Uchikura, Akira Ono, Hiroyuki Yotsuyanagi and Masao Takagi : Built-in Test Circuit for Opens at Interconnects between Dies inside SiPs, Proceedings of ICEP2010, 705-710, Sapporo, Japan, April 2010. ... Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukunori Nakajima and Kozo Kinoshita : Current-Based Testable Design of Level Shifters in Liquid Crystal Display Drivers, Proc. of 2010 15th European Test Symposium, 262, Prague, May 2010. ... Masaki Hashizume, Shohei Kondo and Hiroyuki Yotsuyanagi : Possibility of Logical Error Caused by Open Defects in TSVs, Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, 907-910, Pattaya,Thailand, July 2010. ... Lee Heejin, Hiroyuki Yotsuyanagi and Masaki Hashizume : Lighting Circuit Analysis Method with Measured I-V Characteristics of LEDs, Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, 1262-1265, Pattaya,Thailand, July 2010. ... Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : A Supply Current Testable DAC of Resistor String Type, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 13-16, TianJin,China, March 2011. ... 橋爪 正樹, 加藤 健二, 四柳 浩之 : IEEE1149.1準拠IC間断線の電気検査法, エレクトロニクス実装学会誌, Vol.14, No.2, 99-102, 2011年. ... 橋爪 正樹, 小西 朝陽, 四柳 浩之 : バウンダリスキャンテスト機構を流用する部品実装基板の電気的テストとその可能性, 第25回エレクトロニクス実装学会講演大会, 201-204, 2011年3月. ... 近藤 将平, 四柳 浩之, 橋爪 正樹 : 電磁界シミュレータによるTSVの半断線で生じる故障動作解析, 第25回エレクトロニクス実装学会講演大会, 205-206, 2011年3月. ... 橋爪 正樹, 秦 豊, 四柳 浩之, 三浦 幸也 : 抵抗ラダー型DAC 内MOS 短絡の電流テスト容易化設計, 2011年電子情報通信学会総合大会, 121, 2011年3月. ... Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Fault Analysis of Soft Open Defects in TSVs with Electromagnetic Simulator, Proceedings of ICEP2011, 727-731, Nara, Japan, April 2011. ... Katsuya Manabe, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu and Masaki Hashizume : Estimation of Faulty Effects Caused by a Clack at an Interconnect Line in 90nm ICs, Proceedings of ICEP2011, 737-742, Nara, Japan, April 2011. ... Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Faulty Effect of Soft Open Defect in TSV Caused by Logic Values of Neighboring TSVs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 692-695, Gyeongju, Korea, June 2011. ... Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of Electrical Testing for Lead Opens of QFP ICs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 688-691, Gyeongju, Korea, June 2011. ... Yoshihiko Miyamori, Hiroyuki Yotsuyanagi and Masaki Hashizume : Practical Testability of Supply Current Testable DACs of Resistor Type, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 1015-1018, Gyeongju, Korea, June 2011. ... Lee Heejin, Hiroyuki Yotsuyanagi, Sohn Kyungrak and Masaki Hashizume : Feasibility of Operating Point Estimation in Lighting Circuit with Measured I-V Characteristics of LEDs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 1026-1029, Gyeongju, Korea, June 2011. ... 橋爪 正樹, 秦 豊, 四柳 浩之, 三浦 幸也 : デコーダ型 DA 変換器の電流テスト容易化設計, 電気関係学会四国支部連合大会講演論文集, 118, 2011年9月. ... (名) Widianto, Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Feasibility of Open Lead Detection with Built-in Current Sensor, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 119, Sep. 2011. ... 高嶋 理恵, 高木 正夫, 月本 功, 小野 安季良, 橋爪 正樹 : 検査用内部電極からの交流電界印加時の電源電流テスト による CMOS LSI の開放故障検出, 電気関係学会四国支部連合大会講演論文集, 129, 2011年9月. ... 西川 大樹, 富田 泰基, 月本 功, 高木 正夫, 四柳 浩之, 橋爪 正樹 : 電流テストによる CMOS LSI のリード浮き検出に対する低消費電流化の影響, 電気関係学会四国支部連合大会講演論文集, 130, 2011年9月. ... 真鍋 克也, 四柳 浩之, 橋爪 正樹 : メタル配線の完全断線時の出力電圧推定モデル, 電気関係学会四国支部連合大会講演論文集, 138, 2011年9月. ... Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : A Supply Current Testable Register String DAC of Decoder Type, Proc. of 11th International Symposium on Communications and Information Technologies, 58-63, China, Hangzhou, Oct. 2011. ... 七條 香緒莉, 福田 恵理, 橋爪 正樹, 細野 裕希, 勢井 宏義 : 視覚誘発電位測定用LED刺激装置の開発, --- 情動と光波長感受性の関連性解明に向けて ---, (誌名), 2011年10月. ... Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Propagation Delay Analysis of a Soft Open Defect inside a TSV, Transactions of The Japan Institute of Electronics Packaging, Vol.4, No.1, 119-126, 2011. ... (名) Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi and Masaki Hashizume : A Built-in Test Circuit for Open Defects at Interconnects between Dies in 3D ICs, International 3D System Integration Conference, P-2-31-1-P-2-31-5, Osaka, Feb. 2012. ... Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Supply Current Testing of Open Defects at Interconnects in 3D ICs with IEEE 1149.1 Architecture, International 3D System Integration Conference, 8-2-1-8-2-6, Osaka, Feb. 2012. ... 小西 朝陽, 四柳 浩之, 橋爪 正樹 : IC接続部断線の電気的検査を可能にする組み込み型検査用回路, 第26回エレクトロニクス実装学会講演大会, (巻), (号), 166-167, 2012年3月. ... 小野 安季良, 四柳 浩之, 高木 正夫, 橋爪 正樹 : QFP ICの半断線故障に対する電流テスト検査法, 第26回エレクトロニクス実装学会講演大会, (巻), (号), 168-169, 2012年3月. ... 小西 朝陽, 四柳 浩之, 橋爪 正樹 : ESD入力保護能力を低下させないIC間断線の電気的検査用回路, 電子情報通信学会総合大会講演論文集, D-10-4, 2012年3月. ... 山下 淳, 樹下 行三, 四柳 浩之, 橋爪 正樹 : 隣接線を考慮したパターン併合によるオープン故障用テストパターン生成, 電子情報通信学会総合大会講演論文集, D-10-3, 2012年3月. ... Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : An Electrical Test Circuit for Detecting Interconnect Open Defects in 3D ICs, Proceedings of ICEP2012, 88-93, Tokyo, Japan, April 2012. ... Shingo Saijo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : Testable Design of CMOS Image Pixel Circuits for Electrical Testing, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, D-W2-04-1-D-W2-04-4, Sapporo, July 2012. ... Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Sensor for IDDT Testing of CMOS ICs, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, E-M2-05-1-E-M2-05-4, Sapporo, July 2012. ... Takahashi Hiroshi, Higami Yoshinobu, Yamazaki Koji, Tsutsumi Toshiyuki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation for Resistive Open Faults with Considering Adjacent Lines, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, P-T2-06-1-P-T2-06-4, Sapporo, July 2012. ... Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Test Circuit for Supply Current Testing of Open Defects at Interconnects in 3D ICs, Proc. of 4-th Electronics System Integration Technologies Conference(ESTC 2012), PA21.1_1-PA21.1_6, Amsterdam, Sep. 2012. ... Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi : Electrical Interconnect Testing of Open Defects in Assembled PCBs Utilizing IEEE 1149.1 Test Mechanism, International Test Conference 2012, PO1, Anaheim, Nov. 2012. ... Masaki Hashizume, Shohei Kondo, Ei Haraguchi, Hiroyuki Yotsuyanagi, Tetsuo Tada and Zvi Roth : Output Voltage Estimation Method of Hard Open TSV in 3D ICs, Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, 6.1.1-6.1.5, Niigata, Nov. 2012. ... Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : On Detectability Analysis of Open Faults Using SAT-based Test Pattern Generation Considering Adjacent Lines, Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, 2.1.1-2.1.6, Niigata, Nov. 2012. ... Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Electrical Test Method for Interconnect Open Defects in 3D ICs, Transactions of The Japan Institute of Electronics Packaging, Vol.5, No.1, 26-33, 2012. ... (名) Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Zvi Roth and Masaki Hashizume : A Built-in Electrical Test Circuit for Interconnect tests in Assembled PCBs, Proc. of IEEE CPMT Symposium Japan 2012, 201-204, Kyoto, Dec. 2012. ... 橋爪 正樹 : 教育現場から見たボード検査への期待, エレクトロニクス実装学会誌, Vol.16, No.1, 25-29, 2013年1月. ... (名) Widianto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Size Reduction of a Built-in Test Circuit for Locating Open Interconnects in 3D ICs, Proc. of International Conference on Electronics, Information and Communication, 302-303, Bali, Indonesia, Feb. 2013. ... 橋爪 正樹, 芥川 正武, Lu Shyue-Kung, 四柳 浩之 : IEEE1149.1検査機構を用いた双方向信号線の電気テスト法, 第27回エレクトロニクス実装学会講演大会, 55-56, 2013年3月. ... 小野 安季良, 高木 正夫, 四柳 浩之, 橋爪 正樹 : パッケージ内に電極を内蔵したICの入力部断線の交流電界印加時の電流テスト, 第27回エレクトロニクス実装学会講演大会, 53-54, 2013年3月. ... Masaki Hashizume, Masatake Akutagawa, Shyue-Kung Lu and Hiroyuki Yotsuyanagi : Electrical Test Method of Open Defects at Bi-directional Interconnects in 3D ICs, Proceedings of ICEP2013, 13-18, Osaka, Japan, April 2013. ... Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Defect Detection in Assembled PCBs by Supply Current Testing with Electrodes Embedded inside ICs, Proceedings of ICEP2013, 451-456, Osaka, Japan, April 2013. ... 橋爪 正樹 : TSV故障解析・検査法・検査容易化技術, Electronic Journal Archives, No.727, 1-58, 2013年7月. ... LI Tsu-Lin, Masaki Hashizume and Shyue-Kung LU : An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs, IEICE Transactions on Information and Systems, Vol.E96-D, No.9, 2026-2030, 2013. ... Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testability of Open Defects at Interconnections in 3D ICs with a Built-in Test Circuit for Supply Current Testing, International Test Conference 2013, PO29, Anaheim, Sep. 2013. ... Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masanori Nakamura and Masaki Hashizume : Time-to-Digital Converter Embedded in Boundary-Scan Circuit and Its Application to 3D iC Testing, International Test Conference 2013, PO30, Anaheim, Sep. 2013. ... 梅津 翔一, 橋爪 正樹, 四柳 浩之 : ESD入力保護能力を低下させない検査容易化設計によるIC間配線の電気検査可能性調査, 電気関係学会四国支部連合大会講演論文集, 114, 2013年9月. ... 山下 淳, 四柳 浩之, 橋爪 正樹, 樋上 喜信, 高橋 寛 : SAT 手法による隣接線影響を考慮した 微小遅延故障検査用テストパターン生成に関する一考察, 電気関係学会四国支部連合大会講演論文集, 126, 2013年9月. ... 森 凌太, 橋爪 正樹, 四柳 浩之 : 反転信号のリセットを制御するBASTを用いたテストデータ量削減手法, 電気関係学会四国支部連合大会講演論文集, 127, 2013年9月. ... 花房 世規, 橋爪 正樹, 四柳 浩之 : 設計制約下におけるスキャンチェーン接続順変更によるBAST用テストデータ量削減手法, 電気関係学会四国支部連合大会講演論文集, 128, 2013年9月. ... 松川 翔平, 高橋 寛, 樋上 喜信, 四柳 浩之, 橋爪 正樹 : 抵抗性オープン故障に対する診断用テスト生成, 電気関係学会四国支部連合大会講演論文集, 125, 2013年9月. ... 橋爪 正樹, 小西 朝陽, 四柳 浩之 : 3次元実装IC内ダイ間論理信号線の断線に対する電気テスト用回路, 電子情報通信学会論文誌(C), Vol.J96-C, No.11, 361-370, 2013年. ... Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu : Built-in IDDT Appearance Time Sensor for Detecting Open Faults in 3D IC, Proc. of IEEE CPMT Symposium Japan(ICSJ2013), 247-250, Kyoto, Nov. 2013. ... Ei Haraguchi, Masaki Hashizume, Katsuya Manabe, Hiroyuki Yotsuyanagi, Tetsuo Tada, Shyue-Kung Lu and Zvi Roth : Reduction Method of Number of Electromagnetic Simulation Times for Estimating Output Voltage at Hard Open TSV in 3D IC, Proc. of IEEE CPMT Symposium Japan(ICSJ2013), 251-254, Kyoto, Nov. 2013. ... Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs, Proc.of IEEE 22th Asian Test Symposium, 13-18, Yilan,Taiwan, Nov. 2013. ... Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang and Pony Ning : Fault Scrambling Techniques for Yield Enhancement of Embedded Memories, Proc.of IEEE 22th Asian Test Symposium, 215-220, Yilan,Taiwan, Nov. 2013. ... Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Masaki Hashizume and K. Kewal Saluja : Diagnosing Resistive Open Faults Using Small Delay Fault Simulation, Proc.of IEEE 22th Asian Test Symposium, 79-84, Yilan,Taiwan, Nov. 2013. ... Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : Feasibility of Interconnect Tests of Open Defects in a 3D IC with a Built-in Supply Current Test Circuit, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, I.1.F-1-I.1.F-5, Yilan,Taiwan, Nov. 2013. ... Akira Ono, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Supply Current Test Method for Pin Open Defects in Assembled PCB Circuits, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, I.3.S-1-I.3.S-4, Yilan,Taiwan, Nov. 2013. ... Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On SAT-based Test Generation for Observing Delay Variation Caused by a Resistive Open Fault and Its Adjacent Lines, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, IV.2.F-1-IV.2.F-6, Yilan,Taiwan, Nov. 2013. ... Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.12, 2561-2567, 2013. ... Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : DFT for Supply Current Testing to Detect Open Defects at Interconnects in 3D ICs, Proc. of IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, 60-63, Nara, Dec. 2013. ... 橋爪 正樹, 白石 雄大, 四柳 浩之, Shyue-Kung Lu : 組み込み型電気検査回路によるIC 間容量断線検査, 第28回エレクトロニクス実装学会講演大会, 237-238, 2014年3月. ... 梅津 翔一, 四柳 浩之, 橋爪 正樹 : ICのピン浮きの電気検査用組み込み型電流センサ, 第28回エレクトロニクス実装学会講演大会, 239-240, 2014年3月. ... 梅津 翔一, 四柳 浩之, 橋爪 正樹 : 組み込み型電気検査回路によるIC 間容量断線検査, 2014 年電子情報通信学会総合大会情報・システム講演論文集1, 125, 2014年3月. ... Akira Ono, Hiroyuki Yotsuyanagi and Masaki Hashizume : Pin Open Detection of BGA IC by Supply Current Testing, Proceedings of International Conference on Electronics Packaging 2014, 231-234, Toyama, Japan, April 2014. ... Shoichi Umezu, Masaki Hashizume and Hiroyuki Yotsuyanagi : A Built-in Supply Current Test Circuit for Pin Opens in Assembled PCBs, Proceedings of International Conference on Electronics Packaging 2014, 227-230, Toyama, April 2014. ... Yudai Shiraishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu : Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC, Proc. of International Conference on Electronics Packaging 2014, 235-238, (都市), April 2014. ... Shyue-Kung Lu, Huai-Min Li, Masaki Hashizume, Jin-Hua Hong and Zheng-Ru Tsai : Efficient Test Length Reduction Techniques for Interposer-based 2.5D ICs, Proc. of 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, Hsinchu, Taiwan, April 2014. ... 梅津 翔一, 四柳 浩之, 橋爪 正樹 : 組み込み型電気検査回路によるICのピン浮き検査可能性実験, 第24回マイクロエレクトロニクスシンポジウム論文集, 375-378, 2014年9月. ... Masaki Hashizume, Shohei Suenaga and Hiroyuki Yotsuyanagi : A Built-in Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs, Proc. of the 3rd International Conference on Design and Concurrent Engineering, (都市), Sep. 2014. ... Kousuke Nambara, Shoichi Umezu, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Threshold Value Estimation of Electrical Interconnect, Proc. of IEEE CPMT Symposium Japan 2014, 158-161, (都市), Nov. 2014. ... Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume and Seiji Kajihara : Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories, Proc. of 2014 IEEE 23rd Asian Test Symposium, 137-142, (都市), Nov. 2014. ... Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Threshold Setting of Electrical Test Method for Open Defects at Data Bus in 3D SRAM IC, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 64-68, (都市), Nov. 2014. ... Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On SAT-based Test Generation for Resistive Open Using Delay Variation Caused by Effect of Adjacent Lines, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 49-53, (都市), Nov. 2014. ... Chih-Chan Fang, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Test Pattern Matching Method on BAST Architecture for Test Data Reduction by Controlling Scan Shift, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 130-134, (都市), Nov. 2014. ... Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Supply Current Test Circuit for Electrical Interconnect Tests of 3D ICs, Proc. of IEEE 3D System Integration Conference 2014, O7-1-O7-6, Kinsdale, Ireland, Dec. 2014. ... 伊勢 幸太郎, 山下 淳, 四柳 浩之, 橋爪 正樹, 樋上 喜信, 高橋 寛 : 隣接線の信号遷移を用いる半断線故障による遅延変動の識別可能性について, 第72回FTC研究会資料, 2015年1月. ... Masaki Hashizume : Electrical Interconnect Test Method of 3D ICs, 2015 UT and Taiwan Tech Joint Workshop on Advanced VLSI Design Technologies, Taipei, March 2015. ... Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Switch Circuit for Repairing Defective TSVs in a 3D Stacked Memory IC, Proc. of International Forum on Advanced Technologies 2015, 160-161, Tokushima, March 2015. ... Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin and Masaki Hashizume : Built-in Scrambling Analysis for Yield Enhancement of Embedded Memories, Proc. of International Forum on Advanced Technologies 2015, 44-45, Tokushima, March 2015. ... Shyue-Kung Lu, Cheng-Ju Tsai and Masaki Hashizume : Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories, Proc. of International Forum on Advanced Technologies 2015, 68-69, Tokushima, March 2015. ... 白石 雄大, 橋爪 正樹, 四柳 浩之, 横山 洋之, 多田 哲生, Shyue-Kung Lu : SRAMのデータバス断線の電気検査法のしきい値の決定法, 第29回エレクトロニクス実装学会講演大会, 433-434, 2015年3月. ... 橋爪 正樹, 踊場 明宏, 梅津 翔一, Ashikin Ali Fara Binti, 四柳 浩之, Shyue-Kung Lu : 3次元実装IC内ダイ間配線の電気的抵抗断線検出用回路, 第29回エレクトロニクス実装学会講演大会, 431-432, 2015年3月. ... Akihiro Odoriba, Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Ali Ashikin Binti Fara and Shyue-Kung Lu : A Testable Design for Electrical Interconnect Tests of 3D ICs, Proceedings of 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference, 718-722, Kyoto, Japan, April 2015. ... Shyue-Kung Lu, Shu-Ling Lin, Hao-Wei Lin and Masaki Hashizume : Hybrid Scrambling Technique for Increasing the Fabrication Yield of NROM-Based ROMs, Proc. of 2015 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), (巻), (号), 1-4, Hsinchu, Taiwan, April 2015. ... Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume and Jiann-Liang Chen : Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs, IEEE Transactions on Computers, Vol.64, No.5, 1230-1240, 2015. ... Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Repair Circuit of TSVs in a 3D Stacked Memory IC, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015, 431-434, Seoul, June 2015. ... Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Electrical Test for Open Defects in CMOS ICs by Injected Charge, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015, 653-656, Seoul, June 2015. ... Masaki Hashizume, Singo Saijyo and Hiroyuki Yotsuyanagi : Electrically Testable CMOS Image Pixel Circuit, Proc. of IEEE 2015 European Conference on Circuit Theory and Design, 1-4, Trondheim, Aug. 2015. ... Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test of 3D ICs Made of Dies without ESD Protection Circuits with a Built-in Test Circuit, Proc. of IEEE 3D System Integration Conference 2015, TS8.22.1-TS8.22.5, Sendai, Sep. 2015. ... Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test Method of 3D ICs by Injected Charge Volume, Proc. of IEEE 3D System Integration Conference 2015, TS8.19.1-TS8.19.5, Sendai, Sep. 2015. ... Hiroyuki Yotsuyanagi, Akihiro Fujiwara and Masaki Hashizume : On TSV Array Defect Detection Method Using Two Ring-oscillators Considering Signal Transitions at Adjacent TSVs, Proc. of IEEE 3D System Integration Conference 2015, TS8.24.1-TS8.24.4, (都市), Sep. 2015. ... Akihiro Odoriba, Masaki Hashizume, Shoichi Umezu and Hiroyuki Yotsuyanagi : A Design for Testability with nMOS Switches to Detect Open pins in Assembled PCBs, Proc. of International Design and Concurrent Engineering Conference 2015, 31-1-31-6, Tokushima, Sep. 2015. ... 橋爪 正樹 : 先端半導体の高信頼化を実現する接続破断検出回路技術, (誌名), 2015年9月. ... Kosuke Nanbara, Shoichi Umezu, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Threshold Value Estimation Method for Electrical Interconnect Tests of 3D ICs, IEEE CASS Shikoku and Malaysia Chapters Joint Seminar, Oct. 2015. ... Shyue-Kung Lu, Hao-Wei Lin and Masaki Hashizume : An Enhanced Built-In Self-Repair Technique For Yield And Reliability Improvement Of Embedded Memories, Proc. of 2015 IEEE 11th International Conference on ASIC (ASICON), 1-4, Chengdu, China, Nov. 2015. ... Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test Method of 3D ICs without Boundary Scan Flip Flops, Proc. of IEEE CPMT Symposium Japan 2015, 136-139, Kyoto, Nov. 2015. ... Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Test Circuit for Electrical Interconnect Tests of 3D ICs without Boundary Scan Flip Flops, Proc. of the 16th IEEE Workshop on RTL and High Level Testing, 23-28, Mumbai, Nov. 2015. ... Shyue-Kung Lu, Tsai Cheng-Ju and Masaki Hashizume : Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories, Proc. of 2015 IEEE 24th Asian Test Symposium, 49-54, (都市), Nov. 2015. ... Shyue-Kung Lu, Shu-Chi Yu and Masaki Hashizume : Synergistic Built-in Self-Repair Techniques for Enhancing Fabrication Yield of Embedded Memories, Proc. of International Forum on Advanced Technologies 2016, 59-61, Tokushima, March 2016. ... Masaki Hashizume, Yuki Ikiri, Shoichi Umezu, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Feasibility of Electrical Test for Open Defects at Address Bus in 3D Memory IC, Proc. of International Forum on Advanced Technologies 2016, 51-53, Tokushima, March 2016. ... Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Die Design for Cost reduction of 3F Stacked Memory ICs, Proc. of International Forum on Advanced Technologies 2016, 79-80, Tokushima, March 2016. ... Shyue-Kung Lu, Shu-Chi Yu and Masaki Hashizume : Hybrid Scrambling Technique for Increasing the Fabrication Yield of NROM-Based ROMs, Proc. of International Forum on Advanced Technologies 2016, 207-209, Tokushima, March 2016. ... Ali Ashikin Binti Fara, Akihiro Odoriba, Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests of Capacitive Open Defects at BGA ICs in Assembled PCB, Proc. of International Forum on Advanced Technologies 2016, 229-231, Tokushima, March 2016. ... 宮部 拓海, 四柳 浩之, 橋爪 正樹, Roth Zvi : 組込型DC刺激信号印加回路を用いた電流テストによるICのリード浮き検出の可能性, 第30回エレクトロニクス実装学会春季講演大会, 198-200, 2016年3月. ... FARA ASHIKIN BINTI ALI, 梅津 翔一, 伊喜利 勇貴, 四柳 浩之, 橋爪 正樹, Shyue-Kung Lu : バウンダリスキャンテスト回路を有しないICの電流テストによるリード浮き検出法, 第30回エレクトロニクス実装学会春季講演大会, 195-197, 2016年3月. ... Takumi Miyabe, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : A Built-in Electrical Test Circuit for Detecting Open Leads in Assembled PCB Circuits with RC Integrator, Proceedings of International Conference on Electronics Packaging 2016, 451-455, Sapporo, April 2016. ... 橋爪 正樹, 伊喜利 勇貴, 小西 朝陽, 四柳 浩之, Shyue-Kung Lu : バウンダリスキャンテスト機構を用いたはんだ接合部の電気検査法とその組込型検査回路, エレクトロニクス実装学会誌, Vol.19, No.3, 161-165, 2016年. ... Shyue-Kung Lu, Cheng-Ju Tsai and Masaki Hashizume : Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.24, No.8, 2726-2734, 2016. ... Masashi Okamoto, Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : A Built-in Test Circuit to Monitor Changing Process of Resistive Open Defects in 3D ICs, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016, 295-298, Okinawa, July 2016. ... Kouhei Ohtani, Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Test Circuit for Injected Charge Tests of Open Defects in CMOS ICs, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016, 291-294, Okinawa, July 2016. ... Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokiyama, Tetsuo Tada and Shyue-Kung Lu : Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC, Proc. of International Design and Concurrent Engineering Conference 2016, (巻), (号), Langkawi, Sep. 2016. ... Fara Binti Ali Ashikin, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Proc. of International Design and Concurrent Engineering Conference 2016, (巻), (号), (頁), Langkawi, Sep. 2016. ... (名) Widiant, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu and Zvi Roth : A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs, IEICE Transactions on Information and Systems, Vol.E99-D, No.11, 2723-2733, 2016. ... Masaki Hashizume, Akihiro Odoriba, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Defective Level Monitor of Resistive Open Defects in 3D ICs with Logic Gates, Proc. of IEEE CPMT Symposium Japan 2016, 99-102, Kyoto, Nov. 2016. ... Kouhei Ohtani, Masaki Hashizume, Daisuke Suga, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Power Supply Circuit for Interconnect Tests Based on Injected Charge Volume of 3D IC, Proc. of IEEE CPMT Symposium Japan 2016, 139-140, Kyoto, Nov. 2016. ... Ali Ashikin Binti Fara, Masaki Hashizume, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testability for Resistive Open Defects by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops, Proc. of IEEE CPMT Symposium Japan 2016, 137-138, Kyoto, Nov. 2016. ... Shyue-Kung Lu, Shang-Xiu Zhong and Masaki Hashizume : Enhancement of Flash MemoriesAdaptive ECC Techniques for Yield and Reliability, Proc. of 2016 IEEE 25th Asian Test Symposium, 287-292, Hiroshima, Nov. 2016. ... Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Control Circuit and Observation Conditions for Testing Multiple TSVs Using Boundary Scan Circuit with Embedded TDC, Proc. of the 17th IEEE Workshop on RTL and High Level Testing, 1-3-1-1-3-6, Hiroshima, Nov. 2016. ... Fara Ashikin Binti Ali, Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Capacitive Open Defect Detection by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops, Proc. of the 17th IEEE Workshop on RTL and High Level Testing, 1-2-1-1-2-6, Hiroshima, Nov. 2016. ... 薮井 大輔, 四柳 浩之, 橋爪 正樹 : バウンダリスキャンテスト回路を用いた実装基板のオンライン配線試験法, 第31回エレクトロニクス実装学会春季講演大会, 58-61, 2017年3月. ... 大谷 航平, 菅 大介, 四柳 浩之, 橋爪 正樹 : 電荷注入回数によるIC間配線の試験回路, 第31回エレクトロニクス実装学会春季講演大会, 62-65, 2017年3月. ... Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Test Input Vectors for Detecting Stuck-at Faults at Address and Data Buses in 3D Stacked Memory ICs, Proc. of International Forum on Advanced Technologies 2017, 127-129, Hualien, Taiwan, March 2017. ... Michiya Kanda, Masaki Hashizume, Akihiro Odoriba, Yohei Kakee, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Test Circuit Using A Comparator of Offset Cancel Type for Electrical Interconnect Tests of 3D Stacked ICs, Proc. of International Forum on Advanced Technologies 2017, 233-235, Hualien, Taiwan, March 2017. ... 神原 東風, 四柳 浩之, 橋爪 正樹 : IDDT出現時間差を用いる検査法のための低遷移パターンの故障検出率調査, 電子情報通信学会総合大会講演論文集, 139, 2017年3月. ... Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Capacitive Open Detection in 3D ICs with A Built-in Comparator of Offset Cancellation Type, IEEE 2017 Taiwan and Japan Conference on Circuits and Systems, Okayama, Aug. 2017. ... 薮井 大輔, 四柳 浩之, 橋爪 正樹 : BC1タイプのバウンダリスキャンテスト回路を用いた実装基板のオンライン配線検査法, 第27回マイクロエレクトロニクスシンポジウム講演論文集, 351-354, 2017年8月. ... Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Defect Level Monitor of Resistive Open Defect at Interconnects in 3D ICs by Injected Charge Volume, Proc. of 17th International Symposium on Communications and Information Technologies, 46-50, Cairns, Sep. 2017. ... Yuuya Ohama, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yoshinobu Higami and Hiroshi Takahashi : On Selection of Adjacent Lines in Test Pattern Generation for Delay Faults Considering Crosstalk Effects, Proc. of 17th International Symposium on Communications and Information Technologies, 96-100, Cairns, Sep. 2017. ... Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC, Journal of Telecommunication, Electronic and Computer Engineering, Vol.9, No.3-2, 39-42, 2017. ... Fara Alia Ashikin, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Journal of Telecommunication, Electronic and Computer Engineering, Vol.9, No.3-2, 49-52, 2017. ... Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Current Sensor Made of a Comparator of Offset Cancellation Type for Electrical Interconnect Tests of 3D ICs, Proc. of IEEE CPMT Symposium Japan 2017, 137-138, Kyoto, Nov. 2017. ... Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defects Detected by Interconnect Testing Based on Charge Volume Injected to 3D ICs, Proc. of IEEE CPMT Symposium Japan 2017, 231-234, Kyoto, Nov. 2017. ... Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume and Shyue-Kung Lu : Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs, Proc.of IEEE 26th Asian Test Symposium, 237-242, Taipei, Nov. 2017. ... Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume and Hiroyuki Yotsuyanagi : Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories, Proc.of IEEE 26th Asian Test Symposium, 249-254, Taipei, Nov. 2017. ... Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.12, 2842-2850, 2017. ... Hanna Soneda, Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Kung Shyue LU : Detectable Resistive Open Defects in 3D ICs with Electrical Interconnect Test Circuit Made of Diodes, Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications, 655-658, (都市), March 2018. ... Miyatake Noriko, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama and Tetsuo Tada : Oscillation Frequency Estimation of Ring Oscillator for Interconnect Tests in 3D Stacked ICs, Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications, 659-662, (都市), March 2018. ... Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defect Detection in 3D ICs with a Comparator of Offset Cancellation Type under Process Variation, Proc. of International Forum on Advanced Technologies 2018, P1-11-1-P1-11-3, Tokushima, Japan, March 2018. ... Alia Ashikin Fara, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Proc. of International Forum on Advanced Technologies 2018, P1-12-1-P1-12-3, Tokushima, Japan, March 2018. ... Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effect of Routing in Testing a TSV Array Using Boundary Scan Circuit with Embedded TDC, Proc. of International Forum on Advanced Technologies 2018, P1-13-1-P1-13-3, Tokushima, Japan, March 2018. ... Masaki Hashizume : Health Monitoring of Electronic Circuits in IoT Systems, Proc. of International Forum on Advanced Technologies 2019, 29, Taipei, Taiwan, March 2018. ... Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Design and Evaluation of a TDC Cell Embedded in the Boundary Scan Circuit for Delay Fault Testing of 3D ICs, Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), 110-113, Bangkok, July 2018. ... Ishihara Ken, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defects in 3D Stacked ICs Detected by Electrical Interconnect Testing with a Charge Injector Made of MOS Capacitors, Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), 114-117, Bangkok, July 2018. ... ASHIKIN Fara, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung LU and Zvi ROTH : A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs, IEICE Transactions on Information and Systems, Vol.E101-D, No.8, 2053-2063, 2018. ... Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin and Masaki Hashizume : Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories, Journal of Electronic Testing - Theory and Applications, Vol.34, No.4, 435-446, 2018. ... 神田 道也, (著者), 四柳 浩之, 橋爪 正樹 : 実装基板回路内抵抗断線のバウンダリスキャンテストによる出荷後検出能力評価, 第28回マイクロエレクトロニクスシンポジウム講演論文集, 185-188, 2018年9月. ... Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design, Proc.of IEEE 27th Asian Test Symposium, 7-12, Hefei, Oct. 2018. ... Yuta Matsumoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defect Detection in SoCs by a Test Method Based on Injected Charge Volume after Test Input Application, Proc. of IEEE CPMT Symposium Japan 2018, 141-142, Kyoto, Nov. 2018. ... Michiya Kanda, Daisuke Yabui, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Stand-by Mode Test Method of Interconnects between Dies in 3D ICs with IEEE 1149.1 Test Circuits, Proc. of IEEE CPMT Symposium Japan 2018, 189-192, Kyoto, Nov. 2018. ... 池内 康祐, 神田 道也, 平井 智士, 四柳 浩之, 橋爪 正樹 : バウンダリスキャンテスト回路を用いた待機モード時電気試験を可能にするTAPCの開発, 第33回エレクトロニクス実装学会春季講演大会, 12D1-01-1-12D1-01-4, 2019年3月. ... 菊池 愁也, 新開 颯馬, 四柳 浩之, 橋爪 正樹 : TDC組込型バウンダリスキャン設計を用いる微小遅延故障検査における遅延ばらつき影響調査, 第33回エレクトロニクス実装学会春季講演大会, 12D1-03-1-12D1-03-3, 2019年3月. ... 大塚 諒哉, 四柳 浩之, 橋爪 正樹, Chia-Yu Yao : 微小遅延故障検査への PLL 回路の適用についての一考察, 電子情報通信学会総合大会講演論文集, 44, 2019年3月. ... Shuya Kikuchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Delay Measurement under Delay Variations in Boundary Scan Circuit with Embedded TDC, Proc. 2019 IEEE International Test Conference in Asia, 169-174, Tokyo, Sep. 2019. ... 池内 康祐, 神田 道也, 四柳 浩之, 橋爪 正樹, Shyue-Kung Lu : バウンダリスキャンテストによる3D IC内ダイ間抵抗断線検出可能性調査, 第29回マイクロエレクトロニクスシンポジウム論文集, 127-130, 2019年9月. ... 曽根田 伴奈, 神田 道也, 四柳 浩之, 橋爪 正樹, Shyue-Kung Lu : 電気試験法による実装基板内抵抗断線の出荷後検出法, 第29回マイクロエレクトロニクスシンポジウム論文集, 131-134, 2019年9月. ... Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes, Proc. of The IEEE 2019 International 3D Systems Integration Conference, P4022-1-P4022-5, Sendai, Oct. 2019. ... Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume and Hiroyuki Yotsuyanagi : Fault-Aware Dependability Enhancement Techniques for Flash Memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.28, No.3, 634-645, 2020. ... 知野 遥香, 菊池 愁也, 四柳 浩之, 橋爪 正樹 : TDC 組込み型バウンダリスキャンを用いる信号遅延監視システムの検討, 第34回エレクトロニクス実装学会春季講演大会, 4C1-04-1-4C1-04-3, 2020年3月. ... 長田 奏美, 四柳 浩之, 橋爪 正樹 : 遅延故障検査容易化設計の同時観測経路の選択によるテスト時間短縮, 第34回エレクトロニクス実装学会春季講演大会, 4C1-01-1-4C1-01-3, 2020年3月. ... Kanda Michiya, Masaki Hashizume, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol.10, No.5, 895-907, 2020. ... Sako Fumiya, yuki ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yokoyama Hiroshi and Shyue-Kung Lu : Temperature Sensing with a Relaxation Oscillator in CMOS ICs, Proc. of The 35th International Technical Conference on Circuits/Systems, Computers and Communications, 141-144, (都市), July 2020. ... 硲 文弥, 伊喜利 勇貴, 橋爪 正樹, 四柳 浩之, 横山 洋之, Shyue-Kung Lu : 弛緩発振器を用いた組込み型温度センサによる温度推定の可能性, 電気・電子・情報関係学会四国支部連合大会講演論文集, 9-2, 2020年9月. ... 長田 奏美, 四柳 浩之, 橋爪 正樹 : 遅延故障検査容易化設計を用いる検査対象経路の選択手法, 電気・電子・情報関係学会四国支部連合大会講演論文集, 10-1, 2020年9月. ... 福田 康介, 四柳 浩之, 橋爪 正樹 : 3D IC における遅延故障検査容易化設計用のクロック制御回路について, 電気・電子・情報関係学会四国支部連合大会講演論文集, 10-2, 2020年9月. ... 福田 康介, 四柳 浩之, 橋爪 正樹 : 微小遅延故障検査容易化設計用テストクロック制御回路の検討, 第35回エレクトロニクス実装学会春季講演大会, 18B2-01-1-18B2-01-4, 2021年3月. ... 有元 康滋, 牧野 紘史, 四柳 浩之, 橋爪 正樹 : TDC組込み型バウンダリスキャンの観測セル部分選択による検査時間削減について, 第35回エレクトロニクス実装学会春季講演大会, 18B2-02-1-18B2-02-4, 2021年3月. ... Yuki Ikiri, Fumiya Sako, Masaki Hashizume, Hiroyuki Yotsuyanagi, Lu Shyue-Kung, Yazaki Toru, Ikeda Yasuhiro and Uematsu Yutaka : Open Defect Detection in Assembled Circuit Boards with Built-In Relaxation Oscillators, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol.11, No.6, 931-943, 2021. ... Yuya Okumoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Detectable Resistance Increase of Open Defects in Assembled PCBs by Quiescent Currents through Embedded Diodes, Proc. of 2021 International Conference on Electronics Packaging (ICEP), Tokyo, May 2021. ... 橋爪 正樹 : 電気電子系学科におけるエレクトロニクス実装教育, エレクトロニクス実装学会誌, Vol.24, No.6, 484-487, 2021年9月. ... 片山 翔太, 有元 康滋, 四柳 浩之, 橋爪 正樹 : TDC組込み型バウンダリスキャンの遅延信号観測対象判別回路の設計, 第36回エレクトロニクス実装学会春季講演大会, 215-218, 2022年3月. ... Masao Ohmatsu, Fumiya Sako, Ikiri Yuki, Hiroyuki Yotsuyanagi, Lu Shyue-Kung and Masaki Hashizume : Detectability of Open Defects at Interconnects between Dies in 3D Stacked ICs with Relaxation Oscillators, Proc. of IEEE CPMT Symposium Japan 2022, 94-95, Kyoto, Nov. 2022. ... Ohmatsu Masao, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Masaki Hashizume : Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators, Proc.of IEEE 31st Asian Test Symposium, 49-53, (都市), Nov. 2022. ... Miki Hayato, Eisuke Ohama, Hiroyuki Yotsuyanagi and Masaki Hashizume : Evaluation of a PUF Embedded in the Delay Testable Boundary Scan Circuit, Proc. of 2023 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 896-901, Cheju, June 2023. ... 大松 正男, 大寺 佑都, 四柳 浩之, 橋爪 正樹, Shyue-Kung Lu : アナログ素子のみで構成する弛緩発振器によるIC間抵抗断線の検出可能性調査, 第33回マイクロエレクトロニクスシンポジウム論文集, 393-396, 2023年9月. ... Daichi Akamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume : Design of an Efficient PRPG for Testing an Approximate Multiplier Using Truncation, Proc. of 2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), (頁), Okinawa, July 2024. ... Yamahashi Yuya, Ohmatsu Masao, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Masaki Hashizume : Dependence of Threshold Values for Interconnect Testing with Relaxation Oscillators on Unit-to-unit Variations of ICs, 2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Okinawa, July 2024. ... Kenta Sasagawa, Senling Wang, Tatsuya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Yotsuyanagi, Tianming Ni and Xiaoqing Wen : Deep-BMNN: Implementing Sparse Binary Neural Networks in Memory-Based Reconfigurable Processor (MRP), Proc. of 2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), (頁), Okinawa, July 2024. ...
過去3日以内に登録・変更された情報
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Daichi Akamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume : Design of an Efficient PRPG for Testing an Approximate Multiplier Using Truncation, Proc. of 2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), (頁), Okinawa, July 2024.---(Modified by 四柳 浩之 at 2024年9月6日(金) 14:42:13) | ... |
無効な情報 (9件)
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Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita and Takeomi Tamesada : IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment, Proc. of Asian Test Symposium 2004, (巻), (号), 112-117, Kenting, Taiwan, Nov. 2004. Masaki Hashizume, Akira Ono, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Open Lead Detection of CMOS ICs by Low Pressure Probing, Proceedings og International Conference on Electronics Packaging 2007, (巻), (号), 359-364, Tokyo, April 2007. 橋爪 正樹, 一宮 正博, 四柳 浩之, 小野 安季良, 高木 正夫 : QFP ICのリード浮きの電気的検出用回路, エレクトロニクス実装学会講演大会講演論文集, 75-77, 2009年3月. 橋爪 正樹, 一宮 正博, 四柳 浩之, 小野 安季良, 高木 正夫 : QFP ICのリード浮きの電気的検出用回路, 第23回エレクトロニクス実装学会講演大会, (巻), (号), 75-77, 2009年3月. Shiraishi Yudai, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tada Tetsuo and Lu Shyue-Kung : Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC, Proc. of International Conference on Electronics Packaging 2014, 235-238, (都市), April 2014. Yudai Shiraishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu : Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC, Proceedings of International Conference on Electronics Packaging 2014, 235-238, Toyama, Japan, April 2014. Shyue-Kung Lu and Masaki Hashizume : Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield Reliability of Embedded Memories, Proc. of the 24th IEEE Asian Test Symposium 2015, 49-54, Bombay, Nov. 2015. Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Test Circuit for Electrical Interconnect Tests of 3D ICs without Boundary Scan Flip Flops, Proc. of the 16th IEEE Workshop on RTL and High Level Testing, (巻), (号), S2-2-1-S2-2-4, Bombay, Nov. 2015. Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin and Hiroyuki Yotsuyanagi : Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories, Journal of Electronic Testing - Theory and Applications, Vol.34, No.4, 435-446, 2018.
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Number of session users = 1, LA = 0.72, Max(EID) = 414354, Max(EOID) = 1117932.